The search for alternative gate oxide materials has become more vigorous as complementary metal-oxide-semiconductor (CMOS) technology using SiO2 as the gate oxide approaches its fundamental limits. Currently, it is not possible to use SiO2 layers on Si at the thickness required to achieve the next desired level of performance (approximately 10 angstroms) without unacceptably high gate leakage current. Utilizing oxides with dielectric constants greater than that of SiO2 permits larger gate oxide thickness with the same capacitance. However, in addition to a high dielectric constant, the high dielectric constant oxide should exhibit sufficiently large energy band offsets at the interface with Si so that Schottky leakage current is negligible.
Several oxides have been investigated as potential candidates to replace SiO2. One of the most promising thus far is perovskite oxides, such as SrTiO3 (“STO”). These oxides have a high bulk dielectric constant and exhibit a high degree of structural compatibility with Si, making epitaxy possible. It has been demonstrated that single-crystal SrTiO3 thin films can be grown on Si(001) substrates by molecular beam epitaxy (MBE) with interface state densities as low as 6×1010 states/cm2. See, e.g., R. A. McKee et al, Phys. Rev. Lett. 81, p. 3014 (1998) and K. Eisenbeiser et al., Appl. Phys. Lett. 76, p. 1324 (2000). The equivalent dielectric layer thickness of SrTiO3 may be more than ten times less than that of SiO2. Thus, the gate oxide layer thickness can be ten times larger when SiO2 is replaced with SrTiO3, and yet the capacitance can be approximately the same.
Although the SrTiO3/Si structure demonstrates these promising properties, theoretical and experimental evidence indicates that the structure may exhibit significant Schottky electron leakage current. See, e.g., J. Robertson and C. W. Chen, Appl. Phys. Lett. 74, p 1168 (1999) and S. A. Chambers et al., Appl Phys. Lett. 77, p. 1662 (2000), herein incorporated by reference. Referring to FIGS. 1 and 2, the SrTiO3/Si structure exhibits a much smaller conduction band offset (ΔEc1) compared to the valence band offset (ΔEv1) for both n-Si and p-Si structures and, hence, almost the entire band discontinuity resides at the valance band edge. Accordingly, Schottky leakage current may result. It would be desirable to engineer the energy band offset such that appropriate height Schottky barriers exist at both conduction and valence band edges.
Accordingly, a need exists for a semiconductor structure having a gate oxide formed of a high dielectric constant which exhibits low Schottky electron leakage current.
In addition, a need exists for a method of changing the energy band offset at the interface of two crystalline materials to reduce Schottky leakage current.
A need further exists for a method of changing the energy band offset at the interface of two crystalline materials to accommodate specific device applications.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.